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- Develop host side code for Vitis library
- Benchmark the API level performance of the Vitis library
- Collaborate with hardware design team to build a highly efficient software layer for the underline accelerators
- Currently pursuing an undergraduate or master's degree in Computer Science, Electronic Engineering or related fields
- Fluent in Python, Numpy and C++
- Knowledge of using Xilinx XRT/OpenCL runtime library to develop host code
- Knowledge of Xilinx SDAccel tool chain